1. Field of the Invention
The present invention relates to a static semiconductor memory device and, more particularly, to a static semiconductor memory device having a T-type bit line structure.
2. Description of the Related Art
Among conventional static random access memories (hereinafter referred to as SRAM), the mainstream is a memory cell of a high resistance and load type or a TFT load type having four transistors and two loads because it requires a small memory cell layout area. These memory cells, however, have lost their popularities as a power supply voltage of an SRAM has been decreased from 3 V to 2.5 V, 1.8 V and down to 1.5 V because they are not excellent in low-voltage operation characteristics, while a full CMOS cell having six transistors excellent in low-voltage operation characteristics is gaining a popularity.
FIG. 13A is a circuit diagram showing a structure of such a full CMOS memory cell MC. In FIG. 13A, the memory cell MC includes load transistors (P channel MOS transistors) 81 and 82, driver transistors (N channel MOS transistors) 83 and 84 and access transistors (N channel MOS transistor) 85 and 86.
In writing operation, one of a pair of bit lines BL and /BL is brought to a logical high or “H” level and the other is brought to a logical low or “L” level according to write data. Next, a word line WL is brought to a “H” level of a selected level to render the N channel MOS transistors 85 and 86 conductive, so that the levels of the bit line pair BL, /BL are applied to storage nodes N1 and N2, respectively. When the word line WL is brought to a “L” level of a non-selected level, the N channel MOS transistors 85 and 86 are rendered non-conductive, so that the levels of the storage nodes N1 and N2 are latched by the. MOS transistors 81 to 84.
In reading operation, each of the bit line pair BL, /BL is charged to the “H” level. Subsequently, the word line WL is brought to the “H” level of the selected level to render the N channel MOS transistors 85 and 86 conductive, so that according to the levels of the storage nodes N1 and N2, current flows from one of the bit lines BL and /BL to a memory cell ground line MGL through the N channel MOS transistors 85 and 83 or 86 and 84. By comparing the levels of the bit lines BL and /BL, storage data of the memory cell MC is read. When the word line WL is brought to the “L” level of the non-selected level, the N channel MOS transistors 85 and 86 are rendered non-conductive to end data reading.
FIG. 13B is a diagram showing layout of the memory cell MC. On the surface of a silicon substrate, two gate electrodes GE1 and GE2 extending in the Y direction in the figure are formed in parallel to each other, while the word line WL extending in the X direction in the figure is formed. The gate electrodes GE1 and GE2 and the word line WL are formed of a polysilicon layer. From one side to the other side of one end portion of the gate electrodes GE1 and GE2, P-type active layers PA1 and PA2 are formed. From one side to the other of the other end portion of the gate electrode GE1 and from one side to the other of one end portion of the word line WL, an N-type active layer NA1 is formed. From one side to the other of the other end portion of the gate electrode GE2 and from one side to the other of the other end portion of the word line WL, an N-type active layer NA2 is formed.
The P-type active layer PA1 and the gate electrode GE1, and the P-type active layer PA2 and the gate electrode GE2 form the P channel MOS transistors 81 and 82, respectively. The N-type active layer NA1 and the gate electrode GE1, and the N-type active layer NA2 and the gate electrode GE2 form the N channel MOS transistors 83 and 84, respectively. The N-type active layer NA1 and the word line WL, and the N-type active layer NA2 and the word line WL form the N channel MOS transistors 85 and 86, respectively.
Next, a plurality of local lines LL are formed. In FIG. 13B, at a part where the local line LL and the active layer overlap each other, the local line LL and the active layer are conductive to each other. One end portion of each of the active layers PA1 and PA2 (sources of the P channel MOS transistors 81 and 82) is connected to a memory cell power supply line MVL. The memory cell power supply line MVL is formed of a local line LL1.
The other end portion of the P-type active layer PA1 (drain of the P channel MOS transistor 81) is connected to the central part of the N-type active layer NA1 (drains of the N channel MOS transistors 83 and 85) through a local line LL2. The other end portion of the P-type active layer PA2 (drain of the P channel MOS transistor 82) is connected to the central part of the N-type active layer NA2 (drains of the N channel MOS transistors 84 and 86) through a local line LL3. The local lines LL2 and LL3 are connected to the gate electrodes GE2 and GE1 through contact holes CH, CH, respectively.
Furthermore, by a first aluminum line layer, a bit line pair BL, /BL and memory cell ground lines MGL, MGL extending in the Y direction in the figure are formed in parallel to each other. Ones of the ends of the N-type active layers NA1 and NA2 (sources of the N channel MOS transistors 83 and 84) are connected to the memory cell ground lines, MGL, MGL through the contact holes CH, CH. The others of the ends of the N-type active layers NA1 and NA2 (drains of the N channel MOS transistors 85 and 86) are connected to the bit lines BL and /BL through the contact holes CH, CH, respectively.
In such an SRAM, an alien substance might attach to a memory cell MC during manufacturing to cause short circuit (1) between the storage nodes N1 and N2, (2) between the storage node N1 or N2 and the memory cell power supply line MVL, (3) between the storage node N1 or N2 and the memory cell ground line MGL, (4) between the storage node N1 or N2 and the word line WL, (5) between the storage node N1 or N2 and the bit line BL or /BL, (6) between the ,bit line BL or /BL and the word line WL, (7) between the word line WL and the memory cell power supply line MVL, (8) between the bit line BL or /BL and the memory cell ground line MGL and (9) between the memory cell power supply line MVL and the memory cell ground line MGL. In the memory cell MC shown in FIGS. 13A and 13B, since the bit line pair BL, /BL and the memory, cell ground lines MGL, MGL are arranged adjacent and in parallel to each other, short circuit is liable to occur at a part of (8) in particular.
The memory cell MC in which such short circuit occurs fails to operate normally. The SRAM therefore employs a redundant system in which a spare row or column to replace a row or a column containing a defective memory cell MC and a program circuit for programming an address in a defective row or column are provided to, when an address of a defective row or column is input, select the spare row or column in place of the defective row or column, thereby remedying defective products.
Simply replacing a defective row or column with the spare row or column results in that leakage current continues flowing at a shorted part, so that standby current covers a standard value. Therefore, employed is such a method of reducing standby current by providing a fuse between the memory cell power supply line MVL in each row or column and a line of a power supply potential VDD, or a fuse between the bit line pair BL, /BL in each column and the line of the power supply potential VDD and blowing a fuse in a defective row or column.
In a conventional SRAM, however, since a bit line load circuit, a sense amplifier, a gate circuit and a fuse concentrate on an end portion of the bit line pair BL, /BL narrowing an interval between lines of the bit line pair BL, /BL is difficult. Under these circumstances, a so-called T-type bit line structure has been proposed (see Japanese Patent Laying-Open No. 9-162305 and Japanese Patent Laying Open No. 11-306762).
In an SRAM having the T-type bit line structure, a memory array region is divided into a plurality of memory blocks arranged in a plurality of rows and columns. Each memory block, as shown in FIGS. 14A and 14B, includes a plurality of memory cells MC arranged in four rows and a plurality of columns (four columns in the figure). In each memory block, a global word line GWL, a local data input/output line LIO, a bit line signal input/output line BL′, a bit line signal input/output line /BL′, a local data input/output line /LIO and a global column selecting signal GYL extending in the X direction in the figure are formed of a second aluminum line layer. These six lines GWL, LIO, BL′, /BL′, /LIO, and GYL are formed at equal intervals above memory cells MC in four rows included in each memory block. The bit line signal input/output line pair BL′, /BL′ is connected through contact holes CH, CH to a bit line pair BL, /BL of a corresponding column, respectively.
In the SRAM, a bit line load circuit, a sense amplifier, a gate circuit, a fuse and the like can be arranged at an end portion of the bit line signal input/output line pair BL′, /BL′, an interval between the lines of the bit line pair BL, /BL can be reduced to enable reduction in an layout area.
In the longitudinal memory cell MC shown in FIGS. 13A and 13B, however, a ratio of a length of the memory cell MC in a direction of the word line WL to a length of the same in a direction of the bit line pair BL, /BL is approximately 2 to 3. On the other hand, a horizontal memory cell MC is also proposed having a ratio of a length of a memory cell MC in the direction of the word line WL to a length of the same in the direction of the bit line pair BL, /BL is approximately 3 to 1 (see Japanese Patent Laying-Open No. 9-270468). In this horizontal memory cell MC, since the length in the direction of the bit line pair BL, /BL is shorter than that in the direction of the word line WL, it is possible to suppress a signal delay caused by the bit line pair BL, /BL to speed up reading/writing.
In a case where a longitudinal memory cell MC and a horizontal memory cell MC are laid out according to the same design rules, however, while in the longitudinal memory cell MC, 1.5 lines (six lines GWL, LIO, BL′, /BL′, /LIO and GYL per four memory cells) can be arranged per one memory cell row, in the horizontal memory cell MC, 1.0 line can be arranged per one memory cell row at the most. In other words, when a horizontal memory cell MC is adopted, it is impossible to form an SRAM having the T-type bit line structure by adopting such layout as shown in FIGS. 14A and 14B.